Computer Organization and Architecture (10th Edition)

Category: Hardware & DIY
Author: William Stallings


by anonymous   2018-01-29
The cache coherence is handled by the processor and its intrinsics protocols (MESI, MSI, etc). You don't need to worry about cache line issues because programatically you can't change its behavior. Once you garanteed your reads and writes are performed in order the processor will make sure to reflect those changes into the main memory. This [book]( has several information about caching